JTAG Design for Test Training

The course explain design method to improve board fault coverage and localization using BSCAN (JTAG) Tests

  HOME >> Courses and Training >> JTAG Design for Test Training

VEC200: JTAG Design for Test Analysis

The JTAG test strategy makes the Design for Testability (DFT) an essential part of the design process: the GEB enterprise adopting JTAG dramatically improves the prototype testing and debug and benefits from the DFT in terms of testing effort reduction, high test coverage on complex PCB’s, and high diagnostic resolution.

 

To all attendees that will ask will be send for free a permanent BUZZ license and a two months SCRIPT License to perform tests on their prototypes

 

The course explains:

  • Generally, how You have to take care intervene in hardware design to ensure the SCAN Testability.
  • DDR, PLL, FPGA Design cautions and  warnings
  • JTAG Chain signals distribution
  • Fast Flash ISP Programming, software boot precautions
  • Use of JTAG Technologies Engineering Tool to fast prototype tests:
      • Free Tools, Buzz
      • Low cost tools, BuzzPlus
      • Specilized tools, AutoBuzz, Script, Commander
  • Virtual JTAG IP and JTAG Functional Tests
      • VHDL Code Samples
  • Intel® (Altera®) ARM-SOC bring up using LIVE and Commander tools

 

 

 

JTAG Engineering tools Videos

 JTAG LIVE an Engineering BSCAN Tool

Using JTAG Technologies Live tools and Python language in prototype debug (4 Video, English)

The video illustrates how You can use the Jtag Tools in development phase to debug hardware parts of a board, performing manual and automatic connection and stuck tests or functional tests in Python Language.

 

 

 

 

GEB Enterprise S.r.l. • VAT 10190271006
Via Rocca di Papa, 21 - 00179 Roma ITALY •
Ph. +39 06 7827464 - Fax: +39 06 7806894 • info@geb-enterprise.com
web-design

Copyright © 2009 GEB Enterprise S.r.l. All rights reserved.


FEED RSS2.0