+39 06 7827464 info@geb-enterprise.com
GEB Enterprise

GEB Enterprise

Fewe Help Page 2

IP list on fpga board and request form

FEWE HELP: Template Proposal Editor

How to make known your needs

When you start the Template Proposal Editor the following windows will appear on the top of the help windows

Here a list of available IP that you can use….

  • On the left you can open the IP data sheet clicking the “pdf” icon.
  • On the OVERALL column you have to define the quantity of a specific Ip you would have in your system. The OVERALL used gates will be less than the available o the FPGA, the sum of pins IP must be less than 500% of available I/O pins.
  • On the “DEFAULT” column you have to define the IP that will be active and system startup and that can be used simultaneously and bringing out theirs I/O signal trough the FPGA pins. The number of used pins will be less than the available fpga pins
  • On the last rows you can also add IP that aren’t listed in the table, adding some information such as IP name description, number od needed cells, ram bits and pins.

The fewe template proposal editor will compute your needs and will check if the requirements will be fitted in the target board reporting the results on the report table at the bottom of the page.

The last row report synthetically if the need meet the target board available resources with an OK or a WRONG status. The previous rows can help you to fix the potential issues due to too many used resources.

On Notes you can add everything that you want, including any needs that can’t be defined trough the table.

When the status will be OK you can send the template request to GEB  by clicking the send button. GEB will contact you to let you know when the template will be ready, normally few days.

Clicking the extended button more information will be displayed on the windows:

  • On the left additional three columns will be shown the resource usage by each IP
    • The logic elements usage
    • The internal ram usage (inside the FPGA)
    • The external ram usage (outside the FPGA, on the board)
  • In the two columns that appear in the middle of the table  (SET1..SET2 columns) you can optional define others 2 configuration. For them will be guaranteed the possibility of a simultaneous use allowing the routing of all their I/O pins to the FPGA I/O at the same time by the Fewe Fpga Editor.