VME IP and BOARDs Family
VME IP, Intel (Altera) FPGA and a boards set allow a rapid customization of any application
GEB VME RDK (Rapid Development Kit)
A Set of VME Boards and VHDL IP
The VME Bus family have the target to make available at low cost the resources to build a fast prototype of a VMEmaster/slave/controller subsytem. The modularity of the resources, both hardware board and firmware VHDL IP allows to compose many types of application with a low effort and cost.
The application field may be:
- In heterogeneous systems, when you wish to make a soft growth up a mixture of different form factor boards and a flexible bridge could be needed, for instance beetween PC/PXI bus and VME standard/customized bus.
- In components or boards obsolescence replacement.
- In test systems to perform test cycle to an UUT slave board and/or to acknowledge bus cycles from an UUT master board and to perform bus signals check at same time
The GEB-VME board hosts the Fpga, that make available the modular VME IP, the VME Drivers and Receivers, SdRam and Fpga ancillary logic, including a switching power supply, able to generate onboard 3V3 when it isn’t available on P0 connector.
The board is built in two forms factor:
- The first one, has a standard hight 6U but the lenght was reduced to 58mm to allow the connection with a “front end” board that will hosts additional resources such as I/O interfaces or access ports. The front end board will be connected the GEBVME board using a 100 ways, 1.27mm pitch smt connettor that allow to use Fpga I/O signals to make specific interface application.
- The second one, is a non standard, small size form factor (about 83x108mm), well thought to be used inside customized (special) VME bus format, such as military versions of VME bus or in some special, high performances, test equipments. This kind of application often requires both custom form factor and special dedicated signals, like System fail status, System On line, triggers, syncs and soo on. These signals can be simply supported using the fpga I/O signals together to small VHDL code changes.
Users can improve the FPGA logics and local interface using Altera’s tools Quartus, SOPC, QSYS.
The default VME-IP and firmware (VHDL Code) support A32D32 master/slave cycles, interrupt handler, interrupter and SysCon. The related firmware (Monitor), running on NIOSII, allow the user to start all kinds of bus cycles and some macro commands, such as memory test, using RS232, USB, IEEE1149 TAP links.
- 111120A7: VME-N-A32D32 board, A32D32 Master/Slave Board, without Front End, with 2xRS232, DDR, 1149.1 Tap.
- 111120A3: VME-A32D32 board, A32D32 Master/Slave Board, State and Timing Sniffer, Front End with DDR, 2xRS232, USB, 1149.1 Tap.
- 111120A4: VME-A32D32 board, A32D32 Master/Slave Board, State and Timing Sniffer, DDR, Front End with RS232, USB, 1149.1 Integrated Tap Controller.